William Plishker
From ITLWiki
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I am presently working as a post doc at the University of Maryland. I earned my Ph.D. in Electrical Engineering at the University of California, Berkeley in 2006. My research interests include design automation techniques for programmable embedded systems. In 2000, I received my B.S. degree in Computer Engineering from the Georgia Institute of Technology.
Post Doctorate Research
Acceleration of Medical Imaging Applications I have a dual appointment with Prof. Bhattacharyya's group at College Park and Prof. Raj Shekhar in Radiology at UM's School of Medicine in Baltimore. They have been collaborating some for the past year on applying optimization technology to computationally intensive medical imaging problems. One particularly important (and computationally intensive) one is image registration. It takes two 3D images (say a preoperative and a intraoperative image), and aligns them such that the two may be exactly overlaid. In the case of movement or changes in morphology between the two images, elastic image registration can automatically determine how a particular subvolume has changed.
Ph.D. Research
Automated Mapping of Domain Specific Languages onto Application-Specific Multiprocessors
(Advisor Professor Kurt Keutzer) Gigascale Systems Research Center and National Science Foundation CHESS CCR-0225610
Application-specific multiprocessors are capable of high performance implementations while remaining flexible enough to support a range of applications. Architects of these systems achieve high performance through domain-specific optimizations such as multiple processing elements, dedicated logic, and specialized memory and interconnection. However, these features are often introduced at the expense of programming productivity. For application-specific programmable systems to succeed, it is necessary to deliver high performance implementations quickly. Two of the most important and time-consuming steps to arriving at implementations on these platforms are (1) to transform applications descriptions into tasks graphs that may operate in parallel, and (2) to map the resulting description to the architecture. We examine this problem for a popular family of network processors: Intel's IXP2xxx series. We propose a solution to start first with a domain specific language, which permits extraction of parallelism without designer intervention. We then show transformations from this description to a task graph, exposing the computation, data, and communication of the application. We construct a model of the architecture and application, and formulate it as an integer linear programming (ILP) problem. The elements of the task graph are mapped to processing elements, memory, and interconnect of the target architecture. We demonstrate that this method finds optimal solutions with fast run times on representative network applications.
